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Research

Applied research and technology transfer

Ongoing activity across universities, enterprises and institutions on blockchain, Web3, tokenization, privacy and AI, with a focus on operational and measurable results. 66+ publications, 6 patents, collaborations with MIT, EPFL, Northwestern and international industry partners.

Metrics and impact

Publications66+
Citations1 149
h-index19
i10-index31
Patents6
Book chapters6

Metrics source: Google Scholar. Member of HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation) since 2008.

Current focus

Research is oriented towards real-world use cases: architectures, methods and adoption models applicable in enterprise and public contexts.

01

Web3 Hub (Politecnico di Milano)

Project leadership on the adoption of Web3 technologies, digital assets and high-impact experimentation initiatives.

02

Osservatorio Blockchain & Web3

Ongoing research since 2018 on markets, application models and adoption scenarios in Italy and across Europe.

03

Tokenization / RWA

Study of architectures for issuing, managing and tracking digital assets in regulated environments.

04

Privacy and digital identity

Protocols with a privacy-by-design approach, ZKP and interoperable verification mechanisms.

Research areas

Key research areas, from blockchain technologies to dedicated digital systems, including machine learning, sensor networks and energy efficiency.

01

Blockchain and DLT technologies

Blockchain-based systems, smart contracts, cryptographic proof protocols, notarization, tokenization and decentralized applications. Consulting for CONSOB, Florence Court (court-appointed expert), MISE, Assolombarda.

02

Dedicated digital systems and FPGA

Reconfigurable architectures, high-level synthesis for ISL (Iterative Stencil Loop) algorithms, parallel implementations for cryptography, regex matching and multimedia algorithms on FPGA.

03

Machine learning and data analysis

Deep learning, knowledge discovery and data mining techniques applied to in-vitro neural network analysis, public transport optimization and traffic flow prediction.

04

Wireless sensor networks (WSN)

Models and protocol optimization for Body Area Networks, BAN-BAN interference reduction, wearable systems for dysphagia analysis (EPFL/Nestlé project).

05

Energy efficiency

Systems for intelligent management of complex buildings, multi-tenant trigger-action systems, occupancy analysis with iBeacon technologies.

06

Transport and 3D vision

Travel assistants for public transport, network state reconstruction, car sharing flow prediction, vision systems for object recognition and tracking.

Research projects

Selection of projects managed or coordinated as scientific lead or project leader.

International collaborations

Established collaborations with internationally renowned universities and research centers, as well as industry partners in Italy and abroad.

Universities and research centers

MIT EPFL Northwestern University Imperial College London University of Westminster Università di Paderborn Politecnico di Milano Università Statale di Milano Università di Milano-Bicocca

Companies and institutions

Generali ABB CONSOB Deloitte Siemens ST Microelectronics Nestlé NRC Finmeccanica Saipem Telecom Italia ATM Milano AMAT Milano Inpeco Heinz Nixdorf Institut Sony (SCEE) Chinesport Startec

Selected publications

Selection of journal articles and international conference proceedings. For the full list see Google Scholar.

HiPEAC Best Paper Award

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

A. Nacci, V. Rana, I. Beretta, F. Bruschi, D. A. Atienza, D. Sciuto

DAC 2013 — 50th Annual Design Automation Conference, Austin, TX, USA

HiPEAC Best Paper Award

Design Exploration of Energy-Performance Trade-Offs for Wireless Sensor Networks

I. Beretta, F. Rincon, N. Khaled, P. Grassi, V. Rana, D. A. Atienza

DAC 2012 — 49th Annual Design Automation Conference, San Francisco, CA, USA

Top 5 Most Read — IEEE ESL

Island-Based Adaptable Embedded System Design

I. Beretta, V. Rana, D. A. Atienza, D. Sciuto

IEEE Embedded Systems Letters (ESL), Vol. 3, Issue 2, June 2011

DOI: 10.1109/LES.2011.2115991

Tunnelling Trust into the Blockchain: a Merkle Based Proof System for Structured Documents

F. Bruschi, V. Rana, A. Pagani, D. Sciuto

IEEE Access Journal, Vol. 9, pp. 103758-103771

DOI: 10.1109/ACCESS.2020.3028498

Efficient Hardware Design Of Iterative Stencil Loops

V. Rana, I. Beretta, F. Bruschi, A. Nacci, D. A. Atienza, D. Sciuto

IEEE Transactions on Computer-Aided Design (TCAD), Vol. 35, Issue 12, Dec. 2016

DOI: 10.1109/TCAD.2016.2545408

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

I. Beretta, V. Rana, D. A. Atienza, D. Sciuto

IEEE Transactions on Computer-Aided Design (TCAD), Vol. 30, Issue 8, Aug. 2011

DOI: 10.1109/TCAD.2011.2138140

BuildingRules: A Trigger-Action Based System To Manage Complex Commercial Buildings

A. A. Nacci, V. Rana, B. Balaji, P. Spoletini, R. Gupta, D. Sciuto, Y. Agarwal

ACM Transactions on Cyber-Physical Systems (TCPS), Vol. 2, Issue 2, June 2018

DOI: 10.1145/3185500

Mine with it or sell it: the superhashing power dilemma

F. Bruschi, V. Rana, L. Gentile, D. Sciuto

ACM SIGMETRICS Performance Evaluation Review (PER), Vol. 46, Issue 3, Dec. 2018

DOI: 10.1145/3308897.3308954

Criptovalute ed attività criminali: ragioni di un dialogo interdisciplinare

F. Bruschi, F. Di Vizio, V. Rana

Quaderno della Rivista Trimestrale della Scuola di Perfezionamento per le Forze di Polizia, Vol. II/2022

A Privacy Preserving Identification Protocol for Smart Contracts

F. Bruschi, V. Rana, T. Paulon, D. Sciuto

BRAIN Workshop, co-located with IEEE ISCC 2021

All publications on Google Scholar

Patents

6 patents filed as inventor in the fields of blockchain technology and digital security.

Granted 2025PCT

Validazione e certificazione di autenticità di contenuti digitali

Italian patent no. 102023000012651. PCT extension PCT/IB2024/056020. Filing date: 20/06/2023.

Granted 2021

Certificazione di risorse e contenuti online tramite blockchain

Application no. 102019000004151. Title: Sistema e metodo per la certificazione dell'esistenza di un contenuto digitale. Filing date: 21/03/2019.

Filed 2019

Certificazione affidabile di informazioni strutturate in smart contract

Application no. 102019000011688. Title: Sistema e metodo di prova per documenti strutturati. Filing date: 12/07/2019.

Granted 2022

Profilazione di utenti basata su blockchain

Application no. 102020000006832. Management of personal profiling data in a digital flyer distribution system. Filing date: 01/04/2020.

Granted 2022PCT

Valutazione e certificazione dell'apprendimento a distanza

Application no. 102020000007756. PCT extension PCT/IB2021/052956. Blockchain system for automated e-learning management. Filing date: 10/04/2020.

European patentGranted 2023

Scambio, trasferimento e trasporto di asset digitali

European patent EP4092597. Portable device for the exchange and transport of sensitive digital information. Filing date: 18/05/2021.

Book chapters

6 chapters published with Springer, IGI Global and CRC Press.

Design Methodologies for Reconfigurable NoC-based Embedded Systems

V. Rana, F. Bruschi, A. Miele, M. Santambrogio, D. Sciuto

CRC Press, Devices, Circuits, and Systems Series, 2015

Dynamic Reconfigurable NoCs: Characteristics and Performance Issues

V. Rana, M. D. Santambrogio, S. Corbetta

IGI Global Publisher, 2009

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

V. Rana, D. A. Atienza, M. D. Santambrogio, D. Sciuto, G. De Micheli

Springer, VLSI-SoC: Design Methodologies for SoC and SiP, Vol. 313, 2010

An adaptive genetic algorithm for dynamically reconfigurable modules allocation

V. Rana, C. Sandionigi, M. D. Santambrogio, D. Sciuto

Springer, VLSI-SoC: Advanced Topics on Systems on a Chip, Vol. 291, 2009

Review and organization activities

Conference organization

Great Lakes Symposium on VLSI (GLSVLSI) 2011

Local Chair — EPFL, Lausanne, Switzerland

Conference on Field Programmable Logic (FPL) 2010

Local Chair — Politecnico di Milano, Italy

Program Committee (TPC)

FPL 2010–2014 DATE 2012–2014 RAW 2013–2015 EUC 2011–2013 PDP 2014 WRC 2014 CHA'N'GE 2011–2012 DASIP 2011

Reviewer for international journals

IEEE TCAD IEEE TPDPS IEEE ESL IEEE TII ACM TRETS ACM TECS Elsevier JSA Elsevier Integration Elsevier C&EE

Reviewer for international conferences

DAC DATE CODES+ISSS FPL ARC RAW ISVLSI FPT GLSVLSI SPL VLSI-SoC SoC ReConFig EUC

Research roadmap

Google Scholar Propose a research collaboration